Integrated circuit (IC) manufacturers are employing increasingly smaller dimensions and corresponding technologies to make smaller, high-speed semiconductor devices. Along with these advancements, the challenges of maintaining yield and throughput have also increased.
A semiconductor wafer typically includes dies (or chips) separated from each other by scribe lines. Individual chips within the wafer contain circuitry, and the dies are separated by sawing and then are individually packaged. In a semiconductor fabrication process, semiconductor devices on wafers (e.g., an integrated circuit) must be tested at selected steps, or at the end, of the formation so as to maintain and assure device quality. Usually, a testing circuit is simultaneously fabricated on the wafer along with the actual devices. A typical testing method provides a plurality of test pads (commonly referred to as process control monitor pads, or PCM pads) located on the surface scribe lines. The test pads are selected to test different properties of the wafers, such as voltages, drive currents, leakage currents, and the like.
FIG. 1 illustrates test line 10, which may be formed in a scribe line of a wafer, and may include more or fewer test pads (named as TP1 through TP10) than shown in FIG. 1. Each of test pads TP1 through TP10 is connected to a node of the device (or circuit) to be probed. For example, test pads TP1 through TP4 may be used to probe a transistor by connecting to the source, drain, gate, and bulk of the transistor.
A portion of a test scheme is shown in FIG. 2, which is used to test (probe) transistor 22. Drain 24 of transistor 22 is connected to test pad TP1. Sense-measurement-unit (SMU) 12 is connected to test pad TP1 through a test pin, which is symbolized by node 14. Resistor Rc represents the contact resistance between the test pin and test pad TP1. SMU 12 has a forcing node 16, which is connected to the output of amplifier 18, and a sensing node 20, which is connected to the negative input of amplifier 18. To test transistor 22, SMU 12 tries to force a voltage, for example, of 1V to drain 24 of transistor 22, and the current I flowing through transistor 22 is sensed.
Due to the contact resistance Rc, the voltage applied on drain 24 of transistor 22 is reduced. For example, if contact resistance Rc is 30 Ohms, and current I is 1 mA, the voltage drop on the contact resistance Rc is 30 mV. When the voltage at test pin 14 is 1V, the voltage applied on drain 24 drops to 0.97V, which is a three percent shift from the desirable voltage. The sensed current is shifted accordingly, causing the inaccuracy of the evaluation in the performance of transistor 22.
For a 32 nm nominal device having a gate width of about 1 μm and a gate length of about 0.04 μm, the shift in the sensed performance may reach as great as about 10 percent. To make it worse, the contact resistance Rc is affected by various factors, such as the queue-time of the probed wafer, the probe card overdrive, and the probe card quality. As a result, contact resistance Rc may vary in a wide range, making it very difficult to compensate for the inaccuracy of the probe. Accordingly, what is needed in the art is a sensing scheme and structure that may overcome the deficiencies of the prior art.